The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
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Uma unidade de cálculo analógico programável (ACU) é projetada para cálculos vetoriais em tempo contínuo com escala de circuito compacta. Desde nosso estudo inicial, é viável recuperar funções arbitrárias de duas variáveis por meio de regressão vetorial de suporte (SVR) em silício. Neste trabalho, as dimensões da regressão são ampliadas para cálculos vetoriais. No entanto, o custo do hardware e o erro de computação aumentam muito junto com a expansão das dimensões. Uma arquitetura de dois estágios é proposta para organizar múltiplas ACUs para regressão de alta dimensão. O cálculo de vetores de alta dimensão é separado em vários cálculos de vetores de menor dimensão, que são implementados pela combinação livre de diversas ACUs de menor custo. Desta forma, a escala do circuito e o erro de regressão são reduzidos. A ACU de prova de conceito é projetada e simulada em um formato de 0.18μm tecnologia. A partir dos resultados da simulação do circuito, todos os cálculos demonstrados com nove operandos são executados sem ciclos de clock iterativos por 4960 transistores. O erro de cálculo das funções de exemplo está abaixo de 8.7%.
Renyuan ZHANG
Nara Institute of Science and Technology
Takashi NAKADA
Nara Institute of Science and Technology
Yasuhiko NAKASHIMA
Nara Institute of Science and Technology
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Renyuan ZHANG, Takashi NAKADA, Yasuhiko NAKASHIMA, "Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 7, pp. 878-885, July 2019, doi: 10.1587/transfun.E102.A.878.
Abstract: A programmable analog calculation unit (ACU) is designed for vector computations in continuous-time with compact circuit scale. From our early study, it is feasible to retrieve arbitrary two-variable functions through support vector regression (SVR) in silicon. In this work, the dimensions of regression are expanded for vector computations. However, the hardware cost and computing error greatly increase along with the expansion of dimensions. A two-stage architecture is proposed to organize multiple ACUs for high dimensional regression. The computation of high dimensional vectors is separated into several computations of lower dimensional vectors, which are implemented by the free combination of several ACUs with lower cost. In this manner, the circuit scale and regression error are reduced. The proof-of-concept ACU is designed and simulated in a 0.18μm technology. From the circuit simulation results, all the demonstrated calculations with nine operands are executed without iterative clock cycles by 4960 transistors. The calculation error of example functions is below 8.7%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.878/_p
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@ARTICLE{e102-a_7_878,
author={Renyuan ZHANG, Takashi NAKADA, Yasuhiko NAKASHIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation},
year={2019},
volume={E102-A},
number={7},
pages={878-885},
abstract={A programmable analog calculation unit (ACU) is designed for vector computations in continuous-time with compact circuit scale. From our early study, it is feasible to retrieve arbitrary two-variable functions through support vector regression (SVR) in silicon. In this work, the dimensions of regression are expanded for vector computations. However, the hardware cost and computing error greatly increase along with the expansion of dimensions. A two-stage architecture is proposed to organize multiple ACUs for high dimensional regression. The computation of high dimensional vectors is separated into several computations of lower dimensional vectors, which are implemented by the free combination of several ACUs with lower cost. In this manner, the circuit scale and regression error are reduced. The proof-of-concept ACU is designed and simulated in a 0.18μm technology. From the circuit simulation results, all the demonstrated calculations with nine operands are executed without iterative clock cycles by 4960 transistors. The calculation error of example functions is below 8.7%.},
keywords={},
doi={10.1587/transfun.E102.A.878},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 878
EP - 885
AU - Renyuan ZHANG
AU - Takashi NAKADA
AU - Yasuhiko NAKASHIMA
PY - 2019
DO - 10.1587/transfun.E102.A.878
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2019
AB - A programmable analog calculation unit (ACU) is designed for vector computations in continuous-time with compact circuit scale. From our early study, it is feasible to retrieve arbitrary two-variable functions through support vector regression (SVR) in silicon. In this work, the dimensions of regression are expanded for vector computations. However, the hardware cost and computing error greatly increase along with the expansion of dimensions. A two-stage architecture is proposed to organize multiple ACUs for high dimensional regression. The computation of high dimensional vectors is separated into several computations of lower dimensional vectors, which are implemented by the free combination of several ACUs with lower cost. In this manner, the circuit scale and regression error are reduced. The proof-of-concept ACU is designed and simulated in a 0.18μm technology. From the circuit simulation results, all the demonstrated calculations with nine operands are executed without iterative clock cycles by 4960 transistors. The calculation error of example functions is below 8.7%.
ER -