The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, para facilitar o projeto de circuitos assíncronos, propomos um método de conversão de modelos síncronos de nível de transferência de registro (RTL) para modelos RTL assíncronos com implementação de dados agrupados. O método proposto consiste na geração de uma representação intermediária a partir de um determinado modelo RTL síncrono e na geração de um modelo RTL assíncrono a partir da representação intermediária. Isso nos permite lidar com diferentes estilos de representação de modelos RTL síncronos. Usamos a eXtensible Markup Language (XML) como representação intermediária. Além do modelo RTL assíncrono, o método proposto gera um modelo de simulação quando a implementação alvo é um Field Programmable Gate Array e um conjunto de restrições de não otimização para o circuito de controle usado na síntese lógica e síntese de layout. No experimento, demonstramos que o método proposto pode converter modelos RTL síncronos especificados manualmente e obtidos por uma ferramenta de síntese de alto nível em modelos assíncronos.
Shogo SEMBA
the University of Aizu
Hiroshi SAITO
the University of Aizu
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Shogo SEMBA, Hiroshi SAITO, "Conversion from Synchronous RTL Models to Asynchronous RTL Models" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 7, pp. 904-913, July 2019, doi: 10.1587/transfun.E102.A.904.
Abstract: In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.904/_p
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@ARTICLE{e102-a_7_904,
author={Shogo SEMBA, Hiroshi SAITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Conversion from Synchronous RTL Models to Asynchronous RTL Models},
year={2019},
volume={E102-A},
number={7},
pages={904-913},
abstract={In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.},
keywords={},
doi={10.1587/transfun.E102.A.904},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - Conversion from Synchronous RTL Models to Asynchronous RTL Models
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 904
EP - 913
AU - Shogo SEMBA
AU - Hiroshi SAITO
PY - 2019
DO - 10.1587/transfun.E102.A.904
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2019
AB - In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.
ER -