The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Na era do submícron profundo, os atrasos de interconexão estão se tornando um dos fatores mais importantes que podem afetar o desempenho no projeto VLSI. Muitas pesquisas de ponta em síntese de alto nível tentam considerar o efeito dos atrasos de interconexão. Estas pesquisas de fato alcançam melhor desempenho em comparação com as tradicionais que ignoram os atrasos de interconexão. Entretanto, quando aplicações contêm loops grandes, ainda há muito espaço para melhorar o desempenho explorando o paralelismo. Neste artigo, propomos, pela primeira vez, um método para utilizar técnicas de pipeline e levar em consideração os atrasos de interconexão, de modo a melhorar a qualidade da síntese de alto nível. O método proposto possui as duas características a seguir: 1) separa a consideração do atraso de interconexão do atraso de computação e permite transferência e computação simultânea de dados; 2) pertence ao framework de escalonamento módulo, no sentido de que todas as iterações possuem escalonamentos idênticos e são iniciadas periodicamente. Avaliamos nosso método a partir de dois pontos de vista diferentes. Primeiramente, comparamos nosso método com uma síntese de alto nível com reconhecimento de interconexão existente que não utiliza técnicas de pipelining, e os resultados experimentais mostram que nosso método pode obter uma melhoria de desempenho de cerca de 3.4 vezes, em média. Em segundo lugar, comparamos nosso método com uma síntese de pipeline existente que não considera atrasos de interconexão, e os resultados mostram que nosso método pode obter, em média, uma melhoria de desempenho de cerca de 1.5 vezes. Além disso, também avaliamos nossa arquitetura proposta e os resultados experimentais demonstram que ela é melhor que a arquitetura existente em [1].
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Shanghua GAO, Hiroaki YOSHIDA, Kenshu SETO, Satoshi KOMATSU, Masahiro FUJITA, "Interconnect-Aware Pipeline Synthesis for Array-Based Architectures" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 6, pp. 1464-1475, June 2009, doi: 10.1587/transfun.E92.A.1464.
Abstract: In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1464/_p
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@ARTICLE{e92-a_6_1464,
author={Shanghua GAO, Hiroaki YOSHIDA, Kenshu SETO, Satoshi KOMATSU, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Interconnect-Aware Pipeline Synthesis for Array-Based Architectures},
year={2009},
volume={E92-A},
number={6},
pages={1464-1475},
abstract={In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].},
keywords={},
doi={10.1587/transfun.E92.A.1464},
ISSN={1745-1337},
month={June},}
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TY - JOUR
TI - Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1464
EP - 1475
AU - Shanghua GAO
AU - Hiroaki YOSHIDA
AU - Kenshu SETO
AU - Satoshi KOMATSU
AU - Masahiro FUJITA
PY - 2009
DO - 10.1587/transfun.E92.A.1464
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2009
AB - In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].
ER -