The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O efeito indutivo torna-se importante para interconexões globais no chip, como a rede de energia/terra (P/G). Devido à propriedade de localidade da relutância parcial, o inverso da indutância parcial, a extração de relutância parcial baseada em janela tem sido aplicada para estruturas de interconexão em grande escala. Neste artigo, um método eficiente de extração de relutância parcial é proposto para estruturas de grade P/G regulares de grande escala. Com uma técnica de reutilização de blocos, o método proposto aproveita ao máximo a regularidade estrutural da grade P/G. Resultados numéricos demonstram que o método proposto é capaz de lidar eficientemente com uma rede P/G com até cem mil segmentos de fios. É várias dezenas de vezes mais rápido que o método baseado em janela, ao mesmo tempo que gera relutância e resistência parcial dependente da frequência precisa.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Shan ZENG, Wenjian YU, Jin SHI, Xianlong HONG, Chung-Kuan CHENG, "Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 6, pp. 1476-1484, June 2009, doi: 10.1587/transfun.E92.A.1476.
Abstract: Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1476/_p
Copiar
@ARTICLE{e92-a_6_1476,
author={Shan ZENG, Wenjian YU, Jin SHI, Xianlong HONG, Chung-Kuan CHENG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures},
year={2009},
volume={E92-A},
number={6},
pages={1476-1484},
abstract={Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.},
keywords={},
doi={10.1587/transfun.E92.A.1476},
ISSN={1745-1337},
month={June},}
Copiar
TY - JOUR
TI - Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1476
EP - 1484
AU - Shan ZENG
AU - Wenjian YU
AU - Jin SHI
AU - Xianlong HONG
AU - Chung-Kuan CHENG
PY - 2009
DO - 10.1587/transfun.E92.A.1476
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2009
AB - Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.
ER -