The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
No projeto físico VLSI moderno, a enorme escala de integração exige projeto hierárquico e reutilização de IP para lidar com a complexidade do projeto. Além disso, o atraso de interconexão torna-se dominante no desempenho geral do circuito. Esses fatores críticos exigem que alguns módulos sejam colocados ao longo de limites designados para facilitar efetivamente o projeto hierárquico e os problemas relacionados à otimização da interconexão. Neste artigo, as restrições de limite da planta baixa geral são resolvidas suavemente com base na nova representação de Sequência Única (SS). As condições necessárias e suficientes dos ambientes ao longo dos limites especificados de uma planta baixa são propostas e comprovadas. Ao atribuir módulos restritos a salas de limites adequadas, nosso algoritmo proposto sempre garante um código SS viável com restrições de limites apropriadas em cada perturbação. A complexidade de tempo do algoritmo proposto é O(n). Resultados experimentais em benchmarks MCNC mostram eficácia e eficiência do método proposto.
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Kang LI, Juebang YU, Jian LI, "VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 9, pp. 2369-2375, September 2009, doi: 10.1587/transfun.E92.A.2369.
Abstract: In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2369/_p
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@ARTICLE{e92-a_9_2369,
author={Kang LI, Juebang YU, Jian LI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation},
year={2009},
volume={E92-A},
number={9},
pages={2369-2375},
abstract={In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.},
keywords={},
doi={10.1587/transfun.E92.A.2369},
ISSN={1745-1337},
month={September},}
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TY - JOUR
TI - VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2369
EP - 2375
AU - Kang LI
AU - Juebang YU
AU - Jian LI
PY - 2009
DO - 10.1587/transfun.E92.A.2369
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2009
AB - In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.
ER -