The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Propomos um algoritmo de redução de complexidade para decodificação de soma mínima programada em série que reduz o número de nós de verificação a serem processados durante uma iteração. Os nós de verificação a serem ignorados são escolhidos com base na confiabilidade, uma síndrome e um valor de razão de verossimilhança logarítmica (LLR) das mensagens recebidas. O algoritmo proposto é avaliado por simulações de computador e mostrou reduzir a complexidade de decodificação em cerca de 20% em comparação com uma decodificação de soma mínima programada serial convencional com pequena degradação fracionária de decibéis no desempenho de correção de erros.
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Hironori UCHIKAWA, Kohsuke HARADA, "Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 10, pp. 2411-2417, October 2009, doi: 10.1587/transfun.E92.A.2411.
Abstract: We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2411/_p
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@ARTICLE{e92-a_10_2411,
author={Hironori UCHIKAWA, Kohsuke HARADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes},
year={2009},
volume={E92-A},
number={10},
pages={2411-2417},
abstract={We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.},
keywords={},
doi={10.1587/transfun.E92.A.2411},
ISSN={1745-1337},
month={October},}
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TY - JOUR
TI - Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2411
EP - 2417
AU - Hironori UCHIKAWA
AU - Kohsuke HARADA
PY - 2009
DO - 10.1587/transfun.E92.A.2411
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2009
AB - We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.
ER -