The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Como a tecnologia de circuito integrado passou por uma redução contínua para melhorar o desempenho do LSI e reduzir o tamanho do chip, o design para capacidade de fabricação (DFM) e o design para rendimento (DFY) tornaram-se muito importantes. Como um dos métodos DFM/DFY, uma técnica redundante via inserção usa tantas vias quanto possível para conectar os fios metálicos entre diferentes camadas. Neste artigo, nos concentramos em vias redundantes e propomos um método de inserção via redundante eficaz para uso prático para resolver as questões de variabilidade e confiabilidade de fabricação. Primeiramente, são mostrados os resultados da análise estatística para resistência via e via capacitância em alguns layouts físicos reais, e o impacto no atraso do circuito da variação da resistência das vias causada pela variabilidade de fabricação é esclarecido. Em seguida, as funções de avaliação de variação de atraso, eletromigração (EM) e migração de tensão (SM) são definidas e um método prático relativo à redundância via inserção é proposto. Resultados experimentais mostram que o LSI com vias redundantes inseridas pelo nosso método é robusto contra variabilidade de fabricação e problemas de confiabilidade.
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Yuji TAKASHIMA, Kazuyuki OOYA, Atsushi KUROKAWA, "Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 2962-2970, December 2009, doi: 10.1587/transfun.E92.A.2962.
Abstract: As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2962/_p
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@ARTICLE{e92-a_12_2962,
author={Yuji TAKASHIMA, Kazuyuki OOYA, Atsushi KUROKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability},
year={2009},
volume={E92-A},
number={12},
pages={2962-2970},
abstract={As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.},
keywords={},
doi={10.1587/transfun.E92.A.2962},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2962
EP - 2970
AU - Yuji TAKASHIMA
AU - Kazuyuki OOYA
AU - Atsushi KUROKAWA
PY - 2009
DO - 10.1587/transfun.E92.A.2962
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.
ER -