The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste relatório, propomos uma arquitetura VLSI em pipeline de alto desempenho do filtro adaptativo LMS derivada de uma técnica de retemporização com conjunto de corte. A arquitetura proposta possui uma forma peculiar de pipeline com 3 atrasos de adaptação, e a porção do filtro FIR possui uma classe peculiar de forma transposta proporcionando latência de saída e coeficiente de atraso mínimos. Ambos os atrasos, o atraso de adaptação e o atraso de coeficiente, são compensados por uma conversão antecipada. É empregado um novo somador tipo CSA de alta velocidade com 4 entradas e 2 saídas e um pequeno hardware. A arquitetura proposta pode alcançar uma boa propriedade de convergência, alta taxa de amostragem, latência mínima de saída, hardware pequeno e menor dissipação de energia, simultaneamente, e é muito adequada para implementação no VLSI.
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Kyo TAKAHASHI, Shingo SATO, Tadamichi KUDO, Yoshitaka TSUNEKAWA, "High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 633-637, February 2009, doi: 10.1587/transfun.E92.A.633.
Abstract: In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.633/_p
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@ARTICLE{e92-a_2_633,
author={Kyo TAKAHASHI, Shingo SATO, Tadamichi KUDO, Yoshitaka TSUNEKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders},
year={2009},
volume={E92-A},
number={2},
pages={633-637},
abstract={In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.},
keywords={},
doi={10.1587/transfun.E92.A.633},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 633
EP - 637
AU - Kyo TAKAHASHI
AU - Shingo SATO
AU - Tadamichi KUDO
AU - Yoshitaka TSUNEKAWA
PY - 2009
DO - 10.1587/transfun.E92.A.633
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.
ER -