The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É apresentado um projeto de gerador de pulsos de baixa potência usando realização lógica híbrida de uma porta NAND de 3 entradas. A abordagem lógica híbrida encurta com sucesso o caminho crítico ao longo da pilha de transistores de descarga e, assim, reduz o consumo de energia de curto-circuito durante a geração de pulso. A combinação de transistor de passagem e estilos lógicos CMOS completos em um design de porta NAND também ajuda a minimizar o tamanho do transistor necessário, o que também alivia a capacitância de carga da árvore de clock. Os resultados da simulação revelam que, em comparação com trabalhos anteriores, nosso projeto pode alcançar economias de 20.5% e 23%, respectivamente, na área de energia e circuito.
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Jin-Fa LIN, Yin-Tsung HWANG, Ming-Hwa SHEU, "Low Power Pulse Generator Design Using Hybrid Logic" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 6, pp. 1266-1268, June 2010, doi: 10.1587/transfun.E93.A.1266.
Abstract: A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1266/_p
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@ARTICLE{e93-a_6_1266,
author={Jin-Fa LIN, Yin-Tsung HWANG, Ming-Hwa SHEU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Power Pulse Generator Design Using Hybrid Logic},
year={2010},
volume={E93-A},
number={6},
pages={1266-1268},
abstract={A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.},
keywords={},
doi={10.1587/transfun.E93.A.1266},
ISSN={1745-1337},
month={June},}
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TY - JOUR
TI - Low Power Pulse Generator Design Using Hybrid Logic
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1266
EP - 1268
AU - Jin-Fa LIN
AU - Yin-Tsung HWANG
AU - Ming-Hwa SHEU
PY - 2010
DO - 10.1587/transfun.E93.A.1266
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2010
AB - A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.
ER -