The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, a arquitetura VLSI de um decodificador de parâmetros conjuntos é proposta para realizar o cálculo do vetor de movimento (MV), modo de predição intra (IPM) e força de limite (BS) para aplicações H.264/AVC de ultra alta definição. Para esta arquitetura, um pipeline de 64 ciclos por MB com modos de controle simplificados foi projetado para aumentar o rendimento do sistema e reduzir o custo de hardware. Além disso, para poupar largura de banda de memória, os dados que incluem a informação de movimento para a imagem co-localizada e a última linha descodificada são pré-processados antes de serem armazenados na DRAM. Um formato de armazenamento baseado em partição é aplicado para condensar os dados em nível de MB, enquanto o método de compactação baseado em codificação de comprimento variável é utilizado para reduzir o tamanho dos dados em cada partição. Resultados experimentais mostram que nosso projeto é capaz de realizar 3840
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Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO, "A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 8, pp. 1425-1433, August 2010, doi: 10.1587/transfun.E93.A.1425.
Abstract: In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1425/_p
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@ARTICLE{e93-a_8_1425,
author={Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications},
year={2010},
volume={E93-A},
number={8},
pages={1425-1433},
abstract={In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840
keywords={},
doi={10.1587/transfun.E93.A.1425},
ISSN={1745-1337},
month={August},}
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TY - JOUR
TI - A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1425
EP - 1433
AU - Jinjia ZHOU
AU - Dajiang ZHOU
AU - Xun HE
AU - Satoshi GOTO
PY - 2010
DO - 10.1587/transfun.E93.A.1425
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2010
AB - In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840
ER -