The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A precisão do comparador, que muitas vezes é determinada pelo seu deslocamento, é essencial para a resolução do sistema de sinais mistos de alto desempenho. Vários esforços de projeto foram feitos para cancelar ou calibrar o deslocamento do comparador devido a muitos fatores, como variações do processo, ruído térmico do dispositivo e ruído de alimentação referido à entrada. No entanto, um método simples e eficaz para cancelar o deslocamento, aplicando circuitos adicionais sem escarificar a potência, a velocidade e a área, é sempre um desafio. Este trabalho explora uma técnica de controle dinâmico de offset que emprega compensação de carga por controle de temporização. A injeção de carga e a passagem do clock pelo transistor de redefinição de latch são investigadas. Um método simples é proposto para gerar tensão de compensação de deslocamento implementando dois transistores fonte-dreno em curto em cada nó regenerativo com sinais de controle de temporização em suas portas. É descrita uma análise mais aprofundada do princípio da abordagem de compensação de carga baseada no tempo para controle de compensação do comparador. A análise foi verificada fabricando um comparador CMOS 65 V 1.2 GHz de 1 nm que ocupa 25
Xiaolei ZHU
Yanfei CHEN
Masaya KIBUNE
Yasumoto TOMITA
Takayuki HAMADA
Hirotaka TAMURA
Sanroku TSUKAMOTO
Tadahiro KURODA
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Xiaolei ZHU, Yanfei CHEN, Masaya KIBUNE, Yasumoto TOMITA, Takayuki HAMADA, Hirotaka TAMURA, Sanroku TSUKAMOTO, Tadahiro KURODA, "A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2456-2462, December 2010, doi: 10.1587/transfun.E93.A.2456.
Abstract: The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2456/_p
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@ARTICLE{e93-a_12_2456,
author={Xiaolei ZHU, Yanfei CHEN, Masaya KIBUNE, Yasumoto TOMITA, Takayuki HAMADA, Hirotaka TAMURA, Sanroku TSUKAMOTO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology},
year={2010},
volume={E93-A},
number={12},
pages={2456-2462},
abstract={The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
keywords={},
doi={10.1587/transfun.E93.A.2456},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2456
EP - 2462
AU - Xiaolei ZHU
AU - Yanfei CHEN
AU - Masaya KIBUNE
AU - Yasumoto TOMITA
AU - Takayuki HAMADA
AU - Hirotaka TAMURA
AU - Sanroku TSUKAMOTO
AU - Tadahiro KURODA
PY - 2010
DO - 10.1587/transfun.E93.A.2456
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
ER -