The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O modulador delta-sigma (DSM) multiestágio de modelagem de ruído (MASH) é o elemento-chave em um sintetizador de frequência N fracionária. Um método de simplificação de hardware com inversão de subtração é proposto para o projeto do caminho delta em um modulador delta-sigma MASH. O método de inversão de subtração concentra-se na simplificação da unidade somador-subtrator no caminho delta com inversão do sinal de subtração. É alcançado com menor custo de hardware em comparação com as abordagens convencionais. Como resultado, a organização do hardware é regular e fácil de expandir para um design MASH DSM de ordem superior. Detalhes analíticos da forma de implementação e função de custo de hardware com N-ésima configuração de ordem é apresentada. Finalmente, simulações com linguagem de descrição de hardware, bem como dados de síntese, verificaram o método de projeto proposto.
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Pao-Lung CHEN, "Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2616-2620, December 2010, doi: 10.1587/transfun.E93.A.2616.
Abstract: The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2616/_p
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@ARTICLE{e93-a_12_2616,
author={Pao-Lung CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator},
year={2010},
volume={E93-A},
number={12},
pages={2616-2620},
abstract={The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.},
keywords={},
doi={10.1587/transfun.E93.A.2616},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2616
EP - 2620
AU - Pao-Lung CHEN
PY - 2010
DO - 10.1587/transfun.E93.A.2616
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.
ER -