The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma implementação compacta de hardware (H/W) para a cifra de bloco MISTY1, que é um dos algoritmos de criptografia padrão ISO/IEC 18033-3. Ao projetar o H/W compacto, focamos na otimização da implementação das funções FO/FI/FL, que são os principais componentes do MISTY1. Para esta otimização, propomos três novos métodos; reduzindo registros temporários para a função FO, encurtando o caminho crítico para a função FI e fundindo FL/FL-1 funções. De acordo com nossa síntese lógica em uma biblioteca de células padrão CMOS de 0.18 µm baseada em nossos métodos propostos, o tamanho da porta é de 3.4 Kgates, que é o menor até onde sabemos.
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Dai YAMAMOTO, Jun YAJIMA, Kouichi ITOH, "Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 1, pp. 3-12, January 2010, doi: 10.1587/transfun.E93.A.3.
Abstract: This paper proposes a compact hardware (H/W) implementation for the MISTY1 block cipher, which is one of the ISO/IEC 18033-3 standard encryption algorithms. In designing the compact H/W, we focused on optimizing the implementation of FO/FI/FL functions, which are the main components of MISTY1. For this optimization, we propose three new methods; reducing temporary registers for the FO function, shortening the critical path for the FI function, and merging the FL/FL-1 functions. According to our logic synthesis on a 0.18-µm CMOS standard cell library based on our proposed methods, the gate size is 3.4 Kgates, which is the smallest as far as we know.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.3/_p
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@ARTICLE{e93-a_1_3,
author={Dai YAMAMOTO, Jun YAJIMA, Kouichi ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher},
year={2010},
volume={E93-A},
number={1},
pages={3-12},
abstract={This paper proposes a compact hardware (H/W) implementation for the MISTY1 block cipher, which is one of the ISO/IEC 18033-3 standard encryption algorithms. In designing the compact H/W, we focused on optimizing the implementation of FO/FI/FL functions, which are the main components of MISTY1. For this optimization, we propose three new methods; reducing temporary registers for the FO function, shortening the critical path for the FI function, and merging the FL/FL-1 functions. According to our logic synthesis on a 0.18-µm CMOS standard cell library based on our proposed methods, the gate size is 3.4 Kgates, which is the smallest as far as we know.},
keywords={},
doi={10.1587/transfun.E93.A.3},
ISSN={1745-1337},
month={January},}
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TY - JOUR
TI - Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3
EP - 12
AU - Dai YAMAMOTO
AU - Jun YAJIMA
AU - Kouichi ITOH
PY - 2010
DO - 10.1587/transfun.E93.A.3
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2010
AB - This paper proposes a compact hardware (H/W) implementation for the MISTY1 block cipher, which is one of the ISO/IEC 18033-3 standard encryption algorithms. In designing the compact H/W, we focused on optimizing the implementation of FO/FI/FL functions, which are the main components of MISTY1. For this optimization, we propose three new methods; reducing temporary registers for the FO function, shortening the critical path for the FI function, and merging the FL/FL-1 functions. According to our logic synthesis on a 0.18-µm CMOS standard cell library based on our proposed methods, the gate size is 3.4 Kgates, which is the smallest as far as we know.
ER -