The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, é apresentado um transceptor CMOS de 8 nm de 130 bandas e modo duplo de chip único, incluindo conversores A/D/A e filtros digitais com interface LVDS de 312 MHz. Para uma cadeia de transmissores, a arquitetura de modulação linear direta em quadratura é introduzida tanto para W-CDMA/HSDPA (High Speed Uplink Packet Access) quanto para GSM/EDGE. LPFs analógicos de banda base e moduladores de quadratura são comumente usados tanto para GSM quanto para EDGE. Para uma cadeia receptora de conversão direta, blocos ABB (Banda Base Analógica), ou seja, LPFs e VGAs, conversores A/D delta-sigma e filtros FIR são comumente usados para W-CDMA/HSDPA (Acesso de Pacote de Downlink de Alta Velocidade) e GSM/EDGE para reduzir a área do chip. Suas características podem ser reconfiguradas por sequência de controle baseada em registro. A cadeia receptora também inclui canceladores de deslocamento DC de alta velocidade tanto no estágio analógico quanto no digital, e o controlador AGC independente, cujos parâmetros como constante de tempo são programáveis para serem livres de controle DBB (Digital Base-Band). O transceptor também inclui VCOs de amplo alcance e PLLs fracionários, um driver LVDS e receptor para interface digital de alta velocidade de 312 MHz. Os resultados medidos revelam que o transceptor atende às especificações 3GPP para W-CDMA/HSPA (High Speed Packet Access) e GSM/EDGE.
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Hiroshi YOSHIDA, Takehiko TOYODA, Hiroshi TSURUMI, Nobuyuki ITOH, "A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 375-381, February 2010, doi: 10.1587/transfun.E93.A.375.
Abstract: In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.375/_p
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@ARTICLE{e93-a_2_375,
author={Hiroshi YOSHIDA, Takehiko TOYODA, Hiroshi TSURUMI, Nobuyuki ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface},
year={2010},
volume={E93-A},
number={2},
pages={375-381},
abstract={In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.},
keywords={},
doi={10.1587/transfun.E93.A.375},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 375
EP - 381
AU - Hiroshi YOSHIDA
AU - Takehiko TOYODA
AU - Hiroshi TSURUMI
AU - Nobuyuki ITOH
PY - 2010
DO - 10.1587/transfun.E93.A.375
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.
ER -