The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um flash ADC usando técnicas de interpolação (IP) e autocalibração cíclica de fundo. A técnica IP proposta que é uma cascata de capacitor IP e porta IP com comparador dinâmico travado de cauda dupla reduz a não linearidade, o consumo de energia e a área ocupada. A técnica de autocalibração cíclica de fundo suprime periodicamente tensões de incompatibilidade de deslocamento causadas por flutuação estática e flutuação dinâmica devido a mudanças de temperatura e tensão de alimentação. O ADC foi fabricado em tecnologia CMOS 90P1M de 10 nm. Resultados experimentais mostram que o ADC atinge SNDR de 6.07 bits sem calibração e 6.74 bits com calibração de sinal de entrada de até 500 MHz com taxa de amostragem de 600 MSps. Ele dissipa 98.5 mW na alimentação de 1.2 V. FoM é 1.54 pJ/conv.
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Daehwa PAIK, Yusuke ASADA, Masaya MIYAHARA, Akira MATSUZAWA, "An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 402-414, February 2010, doi: 10.1587/transfun.E93.A.402.
Abstract: This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.402/_p
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@ARTICLE{e93-a_2_402,
author={Daehwa PAIK, Yusuke ASADA, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques},
year={2010},
volume={E93-A},
number={2},
pages={402-414},
abstract={This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.},
keywords={},
doi={10.1587/transfun.E93.A.402},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 402
EP - 414
AU - Daehwa PAIK
AU - Yusuke ASADA
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2010
DO - 10.1587/transfun.E93.A.402
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.
ER -