The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É apresentado um novo projeto de detector de transição de sinal usando apenas 8 transistores. O projeto proposto explora habilmente a propriedade de uma transição de estado interno específica para mitigar o problema de degradação de tensão, empregando apenas um transistor extra. É, portanto, capaz de suportar sinais de saída de nível intacto e eliminar o consumo de energia CC no buffer final. O projeto proposto, apresentando baixa complexidade de circuito e baixo consumo de energia, é considerado útil para aplicações em circuitos autotemporizados. Os resultados da simulação mostram que, quando comparados com outros projetos equivalentes baseados em lógica de transistor de passagem, até 46% de economia em energia e 28% em área podem ser alcançados pelo projeto proposto.
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Jin-Fa LIN, Yin-Tsung HWANG, Ming-Hwa SHEU, "A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 4, pp. 843-845, April 2010, doi: 10.1587/transfun.E93.A.843.
Abstract: A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.843/_p
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@ARTICLE{e93-a_4_843,
author={Jin-Fa LIN, Yin-Tsung HWANG, Ming-Hwa SHEU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits},
year={2010},
volume={E93-A},
number={4},
pages={843-845},
abstract={A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.},
keywords={},
doi={10.1587/transfun.E93.A.843},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 843
EP - 845
AU - Jin-Fa LIN
AU - Yin-Tsung HWANG
AU - Ming-Hwa SHEU
PY - 2010
DO - 10.1587/transfun.E93.A.843
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2010
AB - A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.
ER -