The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Matrizes de portas programáveis em campo (FPGAs) são amplamente utilizadas em sistemas de confiabilidade crítica devido à sua capacidade de reconfiguração. No entanto, com o encolhimento do tamanho do dispositivo e o aumento da área da matriz, hoje em dia os FPGAs podem ser profundamente afetados pelos erros induzidos pela eletromigração e radiação. Para melhorar a confiabilidade de sistemas reconfiguráveis baseados em FPGA, uma abordagem de recuperação permanente de falhas usando um modelo de partição de domínio é proposta neste artigo. Na abordagem proposta, a recuperação de falhas do FPGA tolerante a falhas é realizada recarregando uma configuração adequada de um conjunto de múltiplas configurações alternativas com sobreposições. As sobreposições são apresentadas como um conjunto de vetores no modelo de partição de domínio. Para aumentar a confiabilidade, também é apresentado um procedimento técnico no qual o conjunto de vetores é filtrado heuristicamente para que as pequenas sobreposições correspondentes possam ser mescladas em grandes. Resultados experimentais são fornecidos para demonstrar a eficácia da abordagem proposta através da sua aplicação a vários circuitos de referência. Em comparação com abordagens anteriores, a abordagem proposta aumentou o MTTF em até 18.87%.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Lihong SHANG, Mi ZHOU, Yu HU, Erfu YANG, "A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 1, pp. 290-299, January 2011, doi: 10.1587/transfun.E94.A.290.
Abstract: Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.290/_p
Copiar
@ARTICLE{e94-a_1_290,
author={Lihong SHANG, Mi ZHOU, Yu HU, Erfu YANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems},
year={2011},
volume={E94-A},
number={1},
pages={290-299},
abstract={Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.},
keywords={},
doi={10.1587/transfun.E94.A.290},
ISSN={1745-1337},
month={January},}
Copiar
TY - JOUR
TI - A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 290
EP - 299
AU - Lihong SHANG
AU - Mi ZHOU
AU - Yu HU
AU - Erfu YANG
PY - 2011
DO - 10.1587/transfun.E94.A.290
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2011
AB - Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.
ER -