The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
MD5 é um algoritmo criptográfico usado para autenticação. Quando implementado em hardware, o desempenho é afetado pela dependência de dados da função de compactação iterativa. Neste artigo, uma nova descrição funcional é proposta com o objetivo de obter maior rendimento por meio da redução do caminho crítico e da latência. Esta descrição pode ser usada em estruturas semelhantes de outros algoritmos hash, como SHA-1, SHA-2 e RIPEMD-160, que possuem dependência de dados comparáveis. A arquitetura de hardware MD5 proposta atinge uma alta relação rendimento/área, os resultados da implementação em um FPGA são apresentados e discutidos, bem como comparações com trabalhos relacionados.
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Ignacio ALGREDO-BADILLO, Claudia FEREGRINO-URIBE, Rene CUMPLIDO, Miguel MORALES-SANDOVAL, "Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 10, pp. 2519-2523, October 2008, doi: 10.1093/ietisy/e91-d.10.2519.
Abstract: MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.10.2519/_p
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@ARTICLE{e91-d_10_2519,
author={Ignacio ALGREDO-BADILLO, Claudia FEREGRINO-URIBE, Rene CUMPLIDO, Miguel MORALES-SANDOVAL, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description},
year={2008},
volume={E91-D},
number={10},
pages={2519-2523},
abstract={MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.},
keywords={},
doi={10.1093/ietisy/e91-d.10.2519},
ISSN={1745-1361},
month={October},}
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TY - JOUR
TI - Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description
T2 - IEICE TRANSACTIONS on Information
SP - 2519
EP - 2523
AU - Ignacio ALGREDO-BADILLO
AU - Claudia FEREGRINO-URIBE
AU - Rene CUMPLIDO
AU - Miguel MORALES-SANDOVAL
PY - 2008
DO - 10.1093/ietisy/e91-d.10.2519
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2008
AB - MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.
ER -