The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Sabe-se que o teste de circuitos reversíveis é relativamente mais fácil do que os circuitos irreversíveis convencionais, no sentido de que poucos vetores de teste são necessários para cobrir todas as faltas bloqueadas. Este artigo mostra, no entanto, que é NP-difícil gerar um conjunto de testes mínimo completo para faltas presas nos fios de um circuito reversível usando uma redução de tempo polinomial de 3SAT para o problema. Também mostramos limites inferiores não triviais para o tamanho de um conjunto de testes mínimo completo.
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Satoshi TAYU, Shigeru ITO, Shuichi UENO, "On Fault Testing for Reversible Circuits" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 12, pp. 2770-2775, December 2008, doi: 10.1093/ietisy/e91-d.12.2770.
Abstract: It has been known that testing of reversible circuits is relatively easier than conventional irreversible circuits in the sense that few test vectors are needed to cover all stuck-at faults. This paper shows, however, that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit using a polynomial time reduction from 3SAT to the problem. We also show non-trivial lower bounds for the size of a minimum complete test set.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.12.2770/_p
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@ARTICLE{e91-d_12_2770,
author={Satoshi TAYU, Shigeru ITO, Shuichi UENO, },
journal={IEICE TRANSACTIONS on Information},
title={On Fault Testing for Reversible Circuits},
year={2008},
volume={E91-D},
number={12},
pages={2770-2775},
abstract={It has been known that testing of reversible circuits is relatively easier than conventional irreversible circuits in the sense that few test vectors are needed to cover all stuck-at faults. This paper shows, however, that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit using a polynomial time reduction from 3SAT to the problem. We also show non-trivial lower bounds for the size of a minimum complete test set.},
keywords={},
doi={10.1093/ietisy/e91-d.12.2770},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - On Fault Testing for Reversible Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 2770
EP - 2775
AU - Satoshi TAYU
AU - Shigeru ITO
AU - Shuichi UENO
PY - 2008
DO - 10.1093/ietisy/e91-d.12.2770
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2008
AB - It has been known that testing of reversible circuits is relatively easier than conventional irreversible circuits in the sense that few test vectors are needed to cover all stuck-at faults. This paper shows, however, that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit using a polynomial time reduction from 3SAT to the problem. We also show non-trivial lower bounds for the size of a minimum complete test set.
ER -