The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A unidade de intra-predição é uma parte essencial do codec H.264, pois reduz a quantidade de dados a serem codificados ao prever os valores dos pixels (luminância e crominância) de seus blocos vizinhos. Uma implementação de hardware dedicada para a unidade de intra-predição é necessária para codificação e decodificação em tempo real de dados de vídeo de alta resolução. Para desenvolver uma unidade de intra-predição econômica, este artigo propõe uma nova arquitetura de gerador intra-preditor, a parte central da unidade de intra-predição. O gerador intra-preditor proposto permite que a unidade de intra-predição alcance uma redução significativa do ciclo de clock com aproximadamente a mesma contagem de portas, em comparação com o trabalho de Huang [3].
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Sanghoon KWAK, Jinwook KIM, Dongsoo HAR, "A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 7, pp. 2083-2086, July 2008, doi: 10.1093/ietisy/e91-d.7.2083.
Abstract: The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.7.2083/_p
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@ARTICLE{e91-d_7_2083,
author={Sanghoon KWAK, Jinwook KIM, Dongsoo HAR, },
journal={IEICE TRANSACTIONS on Information},
title={A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec},
year={2008},
volume={E91-D},
number={7},
pages={2083-2086},
abstract={The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].},
keywords={},
doi={10.1093/ietisy/e91-d.7.2083},
ISSN={1745-1361},
month={July},}
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TY - JOUR
TI - A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec
T2 - IEICE TRANSACTIONS on Information
SP - 2083
EP - 2086
AU - Sanghoon KWAK
AU - Jinwook KIM
AU - Dongsoo HAR
PY - 2008
DO - 10.1093/ietisy/e91-d.7.2083
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2008
AB - The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].
ER -