The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, propomos um método, denominado PORT-D, para otimizar circuitos lógicos CMOS para reduzir a dissipação média de potência. PORT-D é um método extensional de PORT. Enquanto o PORT reduz a dissipação média de potência no modelo de atraso zero, o PORT-D reduz a dissipação média de potência levando em consideração o atraso do portão. No PORT-D, a dissipação média de potência é estimada pelo método BDD traversal revisado. O método de passagem BDD revisado calcula a atividade de comutação da saída da porta construindo OBDDs sem representar a condição de comutação de uma saída da porta. O PORT-D modifica o circuito para reduzir a dissipação média de potência, onde são encontradas transformações que reduzem a dissipação média de potência utilizando funções permitidas. Resultados experimentais para circuitos de benchmark mostram que o PORT-D reduz a dissipação média de potência mais do que o número de transistores. Além disso, modificamos o PORT-D para ter alta capacidade de redução de potência. No método revisado, denominado PORT-MIX, é implementada uma estratégia de mistura de PORT e PORT-D. Resultados experimentais mostram que o PORT-MIX tem maior capacidade de redução de potência e maior capacidade de otimização de área do que o PORT-D.
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Hiroaki UEDA, Kozo KINOSHITA, "Power Estimation and Reduction of CMOS Circuits Considering Gate Delay" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 1, pp. 301-308, January 1999, doi: .
Abstract: In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_1_301/_p
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@ARTICLE{e82-d_1_301,
author={Hiroaki UEDA, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={Power Estimation and Reduction of CMOS Circuits Considering Gate Delay},
year={1999},
volume={E82-D},
number={1},
pages={301-308},
abstract={In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.},
keywords={},
doi={},
ISSN={},
month={January},}
Copiar
TY - JOUR
TI - Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
T2 - IEICE TRANSACTIONS on Information
SP - 301
EP - 308
AU - Hiroaki UEDA
AU - Kozo KINOSHITA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 1999
AB - In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.
ER -