The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um novo projeto para testar arranjos de portas programáveis em campo (FPGAs) baseados em SRAM. A memória SRAM do FPGA original é modificada para que o FPGA possa ter a capacidade de fazer um loop dos dados de configuração de teste dentro do chip. O teste completo do FPGA é obtido carregando normalmente apenas um dado de configuração de teste cuidadosamente escolhido, em vez de todos os dados de configuração. Os demais dados de configuração necessários são obtidos deslocando o primeiro dentro do chip. Como resultado, o teste fica mais rápido. Este método não precisa de uma grande memória fora do chip para o teste. Os resultados da avaliação comprovam que este método é muito eficaz quando a complexidade dos blocos configuráveis (CLBs) ou o tamanho do chip aumenta.
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Abderrahim DOUMAR, Toshiaki OHMAMEUDA, Hideo ITO, "Fast Testable Design for SRAM-Based FPGAs" in IEICE TRANSACTIONS on Information,
vol. E83-D, no. 5, pp. 1116-1127, May 2000, doi: .
Abstract: This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
URL: https://global.ieice.org/en_transactions/information/10.1587/e83-d_5_1116/_p
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@ARTICLE{e83-d_5_1116,
author={Abderrahim DOUMAR, Toshiaki OHMAMEUDA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Fast Testable Design for SRAM-Based FPGAs},
year={2000},
volume={E83-D},
number={5},
pages={1116-1127},
abstract={This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Fast Testable Design for SRAM-Based FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 1116
EP - 1127
AU - Abderrahim DOUMAR
AU - Toshiaki OHMAMEUDA
AU - Hideo ITO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E83-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2000
AB - This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
ER -