The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, propomos o sistema de raciocínio evolutivo baseado em algoritmos e sua metodologia de projeto. Na metodologia de projeto proposta, as regras de raciocínio por trás dos casos passados em cada tarefa (no banco de dados de cada caso) são extraídas através de algoritmos genéticos e expressas como tabelas verdade (nós as chamamos de 'tabelas verdade evoluídas'). Os circuitos para os sistemas de raciocínio são sintetizados a partir das tabelas verdade evoluídas. O paralelismo em cada tarefa pode ser incorporado diretamente nos circuitos pela implementação de hardware das tabelas verdade evoluídas, de modo que o sistema de raciocínio de alta velocidade com tamanho de hardware pequeno ou aceitável seja alcançado. Desenvolvemos um sistema protótipo usando chips Xilinx Virtex FPGA e o aplicamos ao raciocínio de limite genético (GBR) e ao raciocínio de pronúncia do inglês (EPR), que são tarefas práticas muito importantes no campo da ciência do genoma e do processamento de linguagem, respectivamente. Os sistemas protótipo GBR e EPR são avaliados em termos de precisão de raciocínio, tamanho do circuito e velocidade de processamento, e comparados com as abordagens convencionais na IA paralela e nas redes neurais artificiais. Experimentos de injeção de falhas também são realizados usando o sistema protótipo, e sua alta tolerância a falhas, ou degradação graciosa contra circuitos defeituosos que se adaptam à implementação de hardware usando LSIs em escala wafer, é demonstrada.
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Moritoshi YASUNAGA, Ikuo YOSHIHARA, Jung Hwan KIM, "The Evolutionary Algorithm-Based Reasoning System" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1508-1520, November 2001, doi: .
Abstract: In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1508/_p
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@ARTICLE{e84-d_11_1508,
author={Moritoshi YASUNAGA, Ikuo YOSHIHARA, Jung Hwan KIM, },
journal={IEICE TRANSACTIONS on Information},
title={The Evolutionary Algorithm-Based Reasoning System},
year={2001},
volume={E84-D},
number={11},
pages={1508-1520},
abstract={In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - The Evolutionary Algorithm-Based Reasoning System
T2 - IEICE TRANSACTIONS on Information
SP - 1508
EP - 1520
AU - Moritoshi YASUNAGA
AU - Ikuo YOSHIHARA
AU - Jung Hwan KIM
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.
ER -