The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um novo microprocessador baseado em arquitetura, um processador paralelo dinamicamente programável (DPPP), que consiste em um grande número de ALUs simplificadas (sALU) como blocos de processamento. Todas as sALUs são interconectadas por meio de uma interface de barramento de acesso múltiplo por divisão de código que fornece flexibilidade completa de roteamento, estabelecendo conexões virtualmente por meio de correspondência de código em vez de fios físicos. Este recurso é utilizado posteriormente para obter alto paralelismo e tolerância a falhas. A alta tolerância a falhas é obtida sem as limitações das técnicas convencionais baseadas na fabricação, nem fornecendo elementos sobressalentes. Outra característica do DPPP é sua programação simples, pois pode ser configurado através da compilação de entrada de fórmula numérica usando a interface de programação automática do usuário fornecida. Um protótipo de chip baseado na arquitetura proposta foi implementado em um chip de 4.5 mm
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Boon-Keat TAN, Ryuji YOSHIMURA, Toshimasa MATSUOKA, Kenji TANIGUCHI, "Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1521-1527, November 2001, doi: .
Abstract: This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1521/_p
Copiar
@ARTICLE{e84-d_11_1521,
author={Boon-Keat TAN, Ryuji YOSHIMURA, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface},
year={2001},
volume={E84-D},
number={11},
pages={1521-1527},
abstract={This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
keywords={},
doi={},
ISSN={},
month={November},}
Copiar
TY - JOUR
TI - Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface
T2 - IEICE TRANSACTIONS on Information
SP - 1521
EP - 1527
AU - Boon-Keat TAN
AU - Ryuji YOSHIMURA
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
ER -