The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Apresentamos um rasterizador paralelo escalável baseado em nossa rasterização de scanline intercalada. A sobrecarga de classificação de uma abordagem convencional de renderização paralela baseada em scanline foi estudada e removida pela implementação de um hardware de atribuição de scanline. Todas as vantagens da renderização paralela baseada em scanline são mantidas de modo que uma boa escalabilidade e um pequeno uso de memória sejam alcançados. Nossa arquitetura é avaliada precisamente por uma simulação baseada em eventos discretos, e o desempenho de renderização e a utilização são mostrados para vários rasterizadores. Os resultados da simulação mostram mais de 8 Mtriângulos/s de desempenho com 64 mecanismos de rasterização rodando a 10 MHz.
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Jun Sung KIM, Kyu Ho PARK, "A PC-Based Scalable Parallel Rasterizer Using Interleaved Scanline Rasterization" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 9, pp. 1266-1274, September 2001, doi: .
Abstract: We present a scalable parallel rasterizer based on our interleaved scanline rasterization. The sorting overhead of a conventional scanline-based parallel rendering approach has been studied and removed by implementing a scanline assignment hardware. All advantages of the scanline-based parallel rendering are kept such that a good scalability and a small memory usage are achieved. Our architecture is evaluated precisely by a discrete event-based simulation, and the rendering performance and utilization are shown for a various number of rasterizers. The simulation results show more than 8 Mtriangles/s of performance with 64 rasterization engines running at 10 MHz.
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_9_1266/_p
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@ARTICLE{e84-d_9_1266,
author={Jun Sung KIM, Kyu Ho PARK, },
journal={IEICE TRANSACTIONS on Information},
title={A PC-Based Scalable Parallel Rasterizer Using Interleaved Scanline Rasterization},
year={2001},
volume={E84-D},
number={9},
pages={1266-1274},
abstract={We present a scalable parallel rasterizer based on our interleaved scanline rasterization. The sorting overhead of a conventional scanline-based parallel rendering approach has been studied and removed by implementing a scanline assignment hardware. All advantages of the scanline-based parallel rendering are kept such that a good scalability and a small memory usage are achieved. Our architecture is evaluated precisely by a discrete event-based simulation, and the rendering performance and utilization are shown for a various number of rasterizers. The simulation results show more than 8 Mtriangles/s of performance with 64 rasterization engines running at 10 MHz.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - A PC-Based Scalable Parallel Rasterizer Using Interleaved Scanline Rasterization
T2 - IEICE TRANSACTIONS on Information
SP - 1266
EP - 1274
AU - Jun Sung KIM
AU - Kyu Ho PARK
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2001
AB - We present a scalable parallel rasterizer based on our interleaved scanline rasterization. The sorting overhead of a conventional scanline-based parallel rendering approach has been studied and removed by implementing a scanline assignment hardware. All advantages of the scanline-based parallel rendering are kept such that a good scalability and a small memory usage are achieved. Our architecture is evaluated precisely by a discrete event-based simulation, and the rendering performance and utilization are shown for a various number of rasterizers. The simulation results show more than 8 Mtriangles/s of performance with 64 rasterization engines running at 10 MHz.
ER -