The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
An n-o teste de detecção de falhas travadas pode ser usado não apenas para testes de falhas com atraso, mas também para detecção de falhas não modeladas. Desenvolvemos um circuito BIST híbrido; isto é, um método que consiste em um registrador de deslocamento com rotação parcial e um procedimento que seleciona vetores de teste dos ATPG. Este método de teste pode realizar testes em velocidade com alta cobertura de falhas travadas. Durante o teste em velocidade, um subconjunto dos vetores ATPG é inserido usando um testador de baixa velocidade. Simulações computacionais nos circuitos ISCAS'85, ISCAS'89 e ITC'99 são conduzidas para n = 1, 2, 3, 5, 10 e 15. Os resultados da simulação mostram que a quantidade de vetores de teste pode ser reduzida para uma faixa de 52.3% a 0.9% em comparação com a dos vetores ATPG. Como resultado, o método proposto pode reduzir o custo dos testes em velocidade.
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Kenichi ICHINO, Takeshi ASAKAWA, Satoshi FUKUMOTO, Kazuhiko IWASAKI, Seiji KAJIHARA, "Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1490-1497, October 2002, doi: .
Abstract: An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1490/_p
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@ARTICLE{e85-d_10_1490,
author={Kenichi ICHINO, Takeshi ASAKAWA, Satoshi FUKUMOTO, Kazuhiko IWASAKI, Seiji KAJIHARA, },
journal={IEICE TRANSACTIONS on Information},
title={Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan},
year={2002},
volume={E85-D},
number={10},
pages={1490-1497},
abstract={An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
T2 - IEICE TRANSACTIONS on Information
SP - 1490
EP - 1497
AU - Kenichi ICHINO
AU - Takeshi ASAKAWA
AU - Satoshi FUKUMOTO
AU - Kazuhiko IWASAKI
AU - Seiji KAJIHARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.
ER -