The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, uma técnica útil é proposta para a realização de testes IDDQ de alta velocidade. Usando a técnica, os capacitores de carga das portas lógicas CMOS podem ser carregados rapidamente, cujos valores lógicos de saída mudam de L para H aplicando um vetor de entrada de teste a um circuito em teste. A técnica é aplicada em IDDQ design do sensor e externo IDDQ projeto do sensor. É demonstrado experimentalmente que testes IDDQ de alta velocidade podem ser realizados usando a técnica.
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Masaki HASHIZUME, Teppei TAKEDA, Masahiro ICHIMIYA, Hiroyuki YOTSUYANAGI, Yukiya MIURA, Kozo KINOSHITA, "IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1534-1541, October 2002, doi: .
Abstract: In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1534/_p
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@ARTICLE{e85-d_10_1534,
author={Masaki HASHIZUME, Teppei TAKEDA, Masahiro ICHIMIYA, Hiroyuki YOTSUYANAGI, Yukiya MIURA, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates},
year={2002},
volume={E85-D},
number={10},
pages={1534-1541},
abstract={In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
T2 - IEICE TRANSACTIONS on Information
SP - 1534
EP - 1541
AU - Masaki HASHIZUME
AU - Teppei TAKEDA
AU - Masahiro ICHIMIYA
AU - Hiroyuki YOTSUYANAGI
AU - Yukiya MIURA
AU - Kozo KINOSHITA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.
ER -