The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Foi desenvolvido um sistema de depuração para múltiplos processadores heterogêneos em um único chip. O sistema consiste no circuito de interface de depuração integrado no chip, na placa de circuito de interface entre o chip e o PC e no software de depuração implementado em um PC. Este sistema de depuração foi projetado para um processador de comunicação multimídia, que inclui um núcleo de processador de vídeo original, um processador RISC e um DSP. O processador RISC controla a Unidade de Processamento de Vídeo que inclui um processador de vídeo original e outras funções de hardware. Enquanto estiver no modo de depuração, o depurador externo pode controlar a Unidade de Processamento de Vídeo da mesma maneira que o processador RISC. O circuito de interface baseado em JTAG contém registros para transações de barramento para comandos, endereços e dados a serem gravados, etc. e um sequenciador de transações de barramento. Na verdade, este sistema pode realizar o mesmo controle de transação de barramento que o processador RISC. Ao aplicar o sistema de depuração proposto, a depuração simultânea da Unidade de Processamento RISC e da Unidade de Processamento de Vídeo pode ser realizada. Isso permite que os problemas sejam investigados mais rapidamente e o tempo total necessário para depuração seja reduzido de forma eficiente. Sem esta tecnologia, são necessárias cerca de 19 semanas para depurar o chip, enquanto o uso desta tecnologia permitiu que a depuração fosse concluída em 9 semanas.
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Noriyuki MINEGISHI, Ken-ichi ASANO, Hirokazu SUZUKI, Keisuke OKADA, Takashi KAN, "A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1571-1578, October 2002, doi: .
Abstract: A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1571/_p
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@ARTICLE{e85-d_10_1571,
author={Noriyuki MINEGISHI, Ken-ichi ASANO, Hirokazu SUZUKI, Keisuke OKADA, Takashi KAN, },
journal={IEICE TRANSACTIONS on Information},
title={A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication},
year={2002},
volume={E85-D},
number={10},
pages={1571-1578},
abstract={A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication
T2 - IEICE TRANSACTIONS on Information
SP - 1571
EP - 1578
AU - Noriyuki MINEGISHI
AU - Ken-ichi ASANO
AU - Hirokazu SUZUKI
AU - Keisuke OKADA
AU - Takashi KAN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.
ER -