The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O consumo de energia das plataformas de servidores tem aumentado à medida que aumenta a quantidade de recursos de hardware nelas equipados. Especialmente, a capacidade da DRAM continua a crescer, e não é raro que a DRAM consuma mais energia do que os processadores dos servidores modernos. Portanto, uma redução no consumo de energia DRAM é um desafio crítico para reduzir o consumo de energia no nível do sistema. Embora seja sabido que a melhoria localidade do buffer de linha(RBL) e paralelismo em nível de banco (BLP) é eficaz para reduzir o consumo de energia DRAM, nossa avaliação preliminar em um servidor real demonstra que o RBL é geralmente baixo em 15 benchmarks multithread. Neste artigo, investigamos os padrões de acesso à memória desses benchmarks usando um simulador e observamos que esquemas de intercalação de canal granulado de cache, que são amplamente aplicados a servidores modernos, incluindo múltiplos canais de memória, prejudicam o RBL que cada um dos benchmarks potencialmente possui. Para resolver esse problema, nos concentramos em um esquema de intercalação de canais com granulação de linha e o comparamos com três esquemas de granulação de linha de cache. Nossa avaliação mostra que reduz o consumo de energia DRAM em 16.7%, 12.3% e 5.5% em média (até 34.7%, 28.2% e 12.0%) em comparação com os outros esquemas, respectivamente.
Satoshi IMAMURA
Fujitsu Laboratories Ltd.
Yuichiro YASUI
Kyushu University
Koji INOUE
Kyushu University
Takatsugu ONO
Kyushu University
Hiroshi SASAKI
Columbia University
Katsuki FUJISAWA
Kyushu University
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Satoshi IMAMURA, Yuichiro YASUI, Koji INOUE, Takatsugu ONO, Hiroshi SASAKI, Katsuki FUJISAWA, "Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs" in IEICE TRANSACTIONS on Information,
vol. E101-D, no. 9, pp. 2247-2257, September 2018, doi: 10.1587/transinf.2017EDP7296.
Abstract: The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2017EDP7296/_p
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@ARTICLE{e101-d_9_2247,
author={Satoshi IMAMURA, Yuichiro YASUI, Koji INOUE, Takatsugu ONO, Hiroshi SASAKI, Katsuki FUJISAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs},
year={2018},
volume={E101-D},
number={9},
pages={2247-2257},
abstract={The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.},
keywords={},
doi={10.1587/transinf.2017EDP7296},
ISSN={1745-1361},
month={September},}
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TY - JOUR
TI - Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs
T2 - IEICE TRANSACTIONS on Information
SP - 2247
EP - 2257
AU - Satoshi IMAMURA
AU - Yuichiro YASUI
AU - Koji INOUE
AU - Takatsugu ONO
AU - Hiroshi SASAKI
AU - Katsuki FUJISAWA
PY - 2018
DO - 10.1587/transinf.2017EDP7296
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E101-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2018
AB - The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.
ER -