The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O ataque de canal lateral, como análise de potência simples e análise de potência diferencial (DPA), é um método eficiente para coletar a chave, o que desafia a segurança dos chips criptográficos. O ataque de canal lateral registra o rastreamento de energia do chip criptográfico e especula a chave por meio de análise estatística. Para reduzir a ameaça de ataque de análise de potência, um método inovador baseado na execução aleatória e na randomização de registros é proposto neste artigo. A fim de aumentar a capacidade contra DPA, o método perturba a correspondência entre o traço de potência e os operandos, embaralhando a sequência de execução de dados de forma aleatória e dinâmica e randomizando o caminho de operação de dados para randomizar os registros que armazenam dados intermediários. Experimentos e verificações são feitos na plataforma Sakura-G FPGA. Os resultados mostram que a chave não é revelada mesmo após 2 milhões de traços de energia, adotando o método proposto e apenas 7.23% de sobrecarga de fatias e 3.4% de custo de taxa de transferência são introduzidos. Comparado ao chip desprotegido, aumenta mais de 4000× a medida de divulgação.
Wei GE
Southeast University
Shenghua CHEN
Southeast University
Benyu LIU
Southeast University
Min ZHU
Tsinghua University
Bo LIU
Southeast University
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Wei GE, Shenghua CHEN, Benyu LIU, Min ZHU, Bo LIU, "A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA" in IEICE TRANSACTIONS on Information,
vol. E103-D, no. 5, pp. 1013-1022, May 2020, doi: 10.1587/transinf.2019EDP7308.
Abstract: Side-channel Attack, such as simple power analysis and differential power analysis (DPA), is an efficient method to gather the key, which challenges the security of crypto chips. Side-channel Attack logs the power trace of the crypto chip and speculates the key by statistical analysis. To reduce the threat of power analysis attack, an innovative method based on random execution and register randomization is proposed in this paper. In order to enhance ability against DPA, the method disorders the correspondence between power trace and operands by scrambling the data execution sequence randomly and dynamically and randomize the data operation path to randomize the registers that store intermediate data. Experiments and verification are done on the Sakura-G FPGA platform. The results show that the key is not revealed after even 2 million power traces by adopting the proposed method and only 7.23% slices overhead and 3.4% throughput rate cost is introduced. Compared to unprotected chip, it increases more than 4000× measure to disclosure.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2019EDP7308/_p
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@ARTICLE{e103-d_5_1013,
author={Wei GE, Shenghua CHEN, Benyu LIU, Min ZHU, Bo LIU, },
journal={IEICE TRANSACTIONS on Information},
title={A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA},
year={2020},
volume={E103-D},
number={5},
pages={1013-1022},
abstract={Side-channel Attack, such as simple power analysis and differential power analysis (DPA), is an efficient method to gather the key, which challenges the security of crypto chips. Side-channel Attack logs the power trace of the crypto chip and speculates the key by statistical analysis. To reduce the threat of power analysis attack, an innovative method based on random execution and register randomization is proposed in this paper. In order to enhance ability against DPA, the method disorders the correspondence between power trace and operands by scrambling the data execution sequence randomly and dynamically and randomize the data operation path to randomize the registers that store intermediate data. Experiments and verification are done on the Sakura-G FPGA platform. The results show that the key is not revealed after even 2 million power traces by adopting the proposed method and only 7.23% slices overhead and 3.4% throughput rate cost is introduced. Compared to unprotected chip, it increases more than 4000× measure to disclosure.},
keywords={},
doi={10.1587/transinf.2019EDP7308},
ISSN={1745-1361},
month={May},}
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TY - JOUR
TI - A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA
T2 - IEICE TRANSACTIONS on Information
SP - 1013
EP - 1022
AU - Wei GE
AU - Shenghua CHEN
AU - Benyu LIU
AU - Min ZHU
AU - Bo LIU
PY - 2020
DO - 10.1587/transinf.2019EDP7308
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E103-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2020
AB - Side-channel Attack, such as simple power analysis and differential power analysis (DPA), is an efficient method to gather the key, which challenges the security of crypto chips. Side-channel Attack logs the power trace of the crypto chip and speculates the key by statistical analysis. To reduce the threat of power analysis attack, an innovative method based on random execution and register randomization is proposed in this paper. In order to enhance ability against DPA, the method disorders the correspondence between power trace and operands by scrambling the data execution sequence randomly and dynamically and randomize the data operation path to randomize the registers that store intermediate data. Experiments and verification are done on the Sakura-G FPGA platform. The results show that the key is not revealed after even 2 million power traces by adopting the proposed method and only 7.23% slices overhead and 3.4% throughput rate cost is introduced. Compared to unprotected chip, it increases more than 4000× measure to disclosure.
ER -