The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A memória não volátil (NVM) é uma tecnologia promissora para memória principal de computadores de baixo consumo de energia e alta capacidade. As características dos dispositivos NVM, entretanto, tendem a ser fundamentalmente diferentes daquelas da DRAM (isto é, o dispositivo de memória atualmente usado para a memória principal), devido às diferenças nos princípios das células de memória. Normalmente, a latência de gravação de um dispositivo NVM como PCM e ReRAM é muito maior do que a latência de leitura. A assimetria nas latências de leitura/gravação provavelmente afeta significativamente o desempenho dos aplicativos. Para analisar o comportamento de aplicações executadas em memória principal baseada em NVM, a maioria dos pesquisadores utiliza ferramentas de emulação baseadas em software devido ao número limitado de produtos NVM comerciais. No entanto, essas ferramentas de emulação existentes são muito lentas para emular uma carga de trabalho realista e em grande escala ou muito simplistas para investigar os detalhes do comportamento do aplicativo no NVM com latências assimétricas de leitura/gravação. Este artigo, portanto, propõe um novo mecanismo de emulação NVM que não é apenas leve, mas também ciente de uma lacuna de latência de leitura/gravação na memória principal baseada em NVM. Implementamos o protótipo do mecanismo proposto para os processadores Intel CPU da arquitetura Haswell. Também avaliamos sua precisão e realizamos estudos de caso para benchmarks práticos. Os resultados mostraram que nosso protótipo emulou com precisão as latências de gravação da memória principal baseada em NVM: ele emulou as latências de gravação NVM em uma faixa de 200 ns a 1000 ns com erros insignificantes de 0.2% a 1.1%. Confirmamos que o uso de nosso emulador nos permitiu estimar com êxito o desempenho de cargas de trabalho práticas para memória principal baseada em NVM, enquanto um modelo de emulação leve existente foi mal estimado.
Atsushi KOSHIBA
RIKEN Center for Computational Science
Takahiro HIROFUCHI
National Institute of Advanced Industrial Science and Technology (AIST)
Ryousei TAKANO
National Institute of Advanced Industrial Science and Technology (AIST)
Mitaro NAMIKI
Tokyo University of Agriculture and Technology
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Atsushi KOSHIBA, Takahiro HIROFUCHI, Ryousei TAKANO, Mitaro NAMIKI, "A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 12, pp. 2377-2388, December 2019, doi: 10.1587/transinf.2019PAP0018.
Abstract: Non-volatile memory (NVM) is a promising technology for low-energy and high-capacity main memory of computers. The characteristics of NVM devices, however, tend to be fundamentally different from those of DRAM (i.e., the memory device currently used for main memory), because of differences in principles of memory cells. Typically, the write latency of an NVM device such as PCM and ReRAM is much higher than its read latency. The asymmetry in read/write latencies likely affects the performance of applications significantly. For analyzing behavior of applications running on NVM-based main memory, most researchers use software-based emulation tools due to the limited number of commercial NVM products. However, these existing emulation tools are too slow to emulate a large-scale, realistic workload or too simplistic to investigate the details of application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation mechanism that is not only light-weight but also aware of a read/write latency gap in NVM-based main memory. We implemented the prototype of the proposed mechanism for the Intel CPU processors of the Haswell architecture. We also evaluated its accuracy and performed case studies for practical benchmarks. The results showed that our prototype accurately emulated write-latencies of NVM-based main memory: it emulated the NVM write latencies in a range from 200 ns to 1000 ns with negligible errors from 0.2% to 1.1%. We confirmed that the use of our emulator enabled us to successfully estimate performance of practical workloads for NVM-based main memory, while an existing light-weight emulation model misestimated.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2019PAP0018/_p
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@ARTICLE{e102-d_12_2377,
author={Atsushi KOSHIBA, Takahiro HIROFUCHI, Ryousei TAKANO, Mitaro NAMIKI, },
journal={IEICE TRANSACTIONS on Information},
title={A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies},
year={2019},
volume={E102-D},
number={12},
pages={2377-2388},
abstract={Non-volatile memory (NVM) is a promising technology for low-energy and high-capacity main memory of computers. The characteristics of NVM devices, however, tend to be fundamentally different from those of DRAM (i.e., the memory device currently used for main memory), because of differences in principles of memory cells. Typically, the write latency of an NVM device such as PCM and ReRAM is much higher than its read latency. The asymmetry in read/write latencies likely affects the performance of applications significantly. For analyzing behavior of applications running on NVM-based main memory, most researchers use software-based emulation tools due to the limited number of commercial NVM products. However, these existing emulation tools are too slow to emulate a large-scale, realistic workload or too simplistic to investigate the details of application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation mechanism that is not only light-weight but also aware of a read/write latency gap in NVM-based main memory. We implemented the prototype of the proposed mechanism for the Intel CPU processors of the Haswell architecture. We also evaluated its accuracy and performed case studies for practical benchmarks. The results showed that our prototype accurately emulated write-latencies of NVM-based main memory: it emulated the NVM write latencies in a range from 200 ns to 1000 ns with negligible errors from 0.2% to 1.1%. We confirmed that the use of our emulator enabled us to successfully estimate performance of practical workloads for NVM-based main memory, while an existing light-weight emulation model misestimated.},
keywords={},
doi={10.1587/transinf.2019PAP0018},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies
T2 - IEICE TRANSACTIONS on Information
SP - 2377
EP - 2388
AU - Atsushi KOSHIBA
AU - Takahiro HIROFUCHI
AU - Ryousei TAKANO
AU - Mitaro NAMIKI
PY - 2019
DO - 10.1587/transinf.2019PAP0018
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2019
AB - Non-volatile memory (NVM) is a promising technology for low-energy and high-capacity main memory of computers. The characteristics of NVM devices, however, tend to be fundamentally different from those of DRAM (i.e., the memory device currently used for main memory), because of differences in principles of memory cells. Typically, the write latency of an NVM device such as PCM and ReRAM is much higher than its read latency. The asymmetry in read/write latencies likely affects the performance of applications significantly. For analyzing behavior of applications running on NVM-based main memory, most researchers use software-based emulation tools due to the limited number of commercial NVM products. However, these existing emulation tools are too slow to emulate a large-scale, realistic workload or too simplistic to investigate the details of application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation mechanism that is not only light-weight but also aware of a read/write latency gap in NVM-based main memory. We implemented the prototype of the proposed mechanism for the Intel CPU processors of the Haswell architecture. We also evaluated its accuracy and performed case studies for practical benchmarks. The results showed that our prototype accurately emulated write-latencies of NVM-based main memory: it emulated the NVM write latencies in a range from 200 ns to 1000 ns with negligible errors from 0.2% to 1.1%. We confirmed that the use of our emulator enabled us to successfully estimate performance of practical workloads for NVM-based main memory, while an existing light-weight emulation model misestimated.
ER -