The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Desenvolvemos um cluster PYNQ que consiste em placas Zynq econômicas, chamadas M-KUBOS, que são interconectadas por meio de links seriais GTH de baixo custo e alto desempenho. Para o ambiente de software, empregamos a plataforma de software de código aberto PYNQ. Prevê-se que o cluster PYNQ seja um servidor de computação de borda multiacesso (MEC) para redes móveis 5G. Implementamos o acelerador de inferência ResNet-50 no cluster PYNQ para reconhecimento de imagem de aplicações MEC. Ao estimar o tempo de execução de cada camada ResNet-50, as camadas do ResNet-50 foram divididas em múltiplas placas para que o tempo de execução de cada placa fosse o mais igual possível para um processamento eficiente do pipeline. Devido ao cluster PYNQ no qual os FPGAs foram conectados diretamente por links seriais de alta velocidade, o processamento de fluxo sem gargalos de rede e o processamento de pipeline entre placas foram prontamente realizados. A implementação em 4 placas alcançou desempenho de 292 GOPS, taxa de transferência de 75.1 FPS e eficiência de energia de 7.81 GOPS/W. Ele alcançou velocidade 17 vezes mais rápida e 130 vezes mais eficiência energética em comparação com a implementação na CPU, e 5.8 vezes mais eficiência energética em comparação com a implementação na GPU.
Yasuyu FUKUSHIMA
Keio University
Kensuke IIZUKA
Keio University
Hideharu AMANO
Keio University
FPGA, multi-FPGA, MEC, CNN
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Yasuyu FUKUSHIMA, Kensuke IIZUKA, Hideharu AMANO, "Parallel Implementation of CNN on Multi-FPGA Cluster" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 7, pp. 1198-1208, July 2023, doi: 10.1587/transinf.2022EDP7175.
Abstract: We developed a PYNQ cluster that consists of economical Zynq boards, called M-KUBOS, that are interconnected through low-cost high-performance GTH serial links. For the software environment, we employed the PYNQ open-source software platform. The PYNQ cluster is anticipated to be a multi-access edge computing (MEC) server for 5G mobile networks. We implemented the ResNet-50 inference accelerator on the PYNQ cluster for image recognition of MEC applications. By estimating the execution time of each ResNet-50 layer, layers of ResNet-50 were divided into multiple boards so that the execution time of each board would be as equal as possible for efficient pipeline processing. Owing to the PYNQ cluster in which FPGAs were directly connected by high-speed serial links, stream processing without network bottlenecks and pipeline processing between boards were readily realized. The implementation on 4 boards achieved 292 GOPS performance, 75.1 FPS throughput, and 7.81 GOPS/W power efficiency. It achieved 17 times faster speed and 130 times more power efficiency compared to the implementation on the CPU, and 5.8 times more power efficiency compared to the implementation on the GPU.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2022EDP7175/_p
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@ARTICLE{e106-d_7_1198,
author={Yasuyu FUKUSHIMA, Kensuke IIZUKA, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={Parallel Implementation of CNN on Multi-FPGA Cluster},
year={2023},
volume={E106-D},
number={7},
pages={1198-1208},
abstract={We developed a PYNQ cluster that consists of economical Zynq boards, called M-KUBOS, that are interconnected through low-cost high-performance GTH serial links. For the software environment, we employed the PYNQ open-source software platform. The PYNQ cluster is anticipated to be a multi-access edge computing (MEC) server for 5G mobile networks. We implemented the ResNet-50 inference accelerator on the PYNQ cluster for image recognition of MEC applications. By estimating the execution time of each ResNet-50 layer, layers of ResNet-50 were divided into multiple boards so that the execution time of each board would be as equal as possible for efficient pipeline processing. Owing to the PYNQ cluster in which FPGAs were directly connected by high-speed serial links, stream processing without network bottlenecks and pipeline processing between boards were readily realized. The implementation on 4 boards achieved 292 GOPS performance, 75.1 FPS throughput, and 7.81 GOPS/W power efficiency. It achieved 17 times faster speed and 130 times more power efficiency compared to the implementation on the CPU, and 5.8 times more power efficiency compared to the implementation on the GPU.},
keywords={},
doi={10.1587/transinf.2022EDP7175},
ISSN={1745-1361},
month={July},}
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TY - JOUR
TI - Parallel Implementation of CNN on Multi-FPGA Cluster
T2 - IEICE TRANSACTIONS on Information
SP - 1198
EP - 1208
AU - Yasuyu FUKUSHIMA
AU - Kensuke IIZUKA
AU - Hideharu AMANO
PY - 2023
DO - 10.1587/transinf.2022EDP7175
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2023
AB - We developed a PYNQ cluster that consists of economical Zynq boards, called M-KUBOS, that are interconnected through low-cost high-performance GTH serial links. For the software environment, we employed the PYNQ open-source software platform. The PYNQ cluster is anticipated to be a multi-access edge computing (MEC) server for 5G mobile networks. We implemented the ResNet-50 inference accelerator on the PYNQ cluster for image recognition of MEC applications. By estimating the execution time of each ResNet-50 layer, layers of ResNet-50 were divided into multiple boards so that the execution time of each board would be as equal as possible for efficient pipeline processing. Owing to the PYNQ cluster in which FPGAs were directly connected by high-speed serial links, stream processing without network bottlenecks and pipeline processing between boards were readily realized. The implementation on 4 boards achieved 292 GOPS performance, 75.1 FPS throughput, and 7.81 GOPS/W power efficiency. It achieved 17 times faster speed and 130 times more power efficiency compared to the implementation on the CPU, and 5.8 times more power efficiency compared to the implementation on the GPU.
ER -