The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A alta dissipação de potência durante o teste de varredura geralmente causa perda indevida de rendimento, especialmente para circuitos de baixa potência. Um dos principais motivos é que a queda de IR resultante no modo shift pode corromper os dados de teste. Uma abordagem comum para resolver este problema é o deslocamento parcial, no qual múltiplas cadeias de varredura são formadas e apenas um grupo de cadeias de varredura é deslocado por vez. No entanto, os métodos existentes baseados em deslocamentos parciais sofrem de dois problemas principais: (1) sua estimativa de queda de IR não é suficientemente precisa ou computacionalmente muito cara para ser feita para cada ciclo de deslocamento; (2) o deslocamento parcial é, portanto, aplicado a todos os ciclos de deslocamento, resultando em um longo tempo de teste. Este artigo aborda esses dois problemas com um novo método de mudança de varredura com reconhecimento de queda de IR, apresentando: (1) Estimativa de queda de IR baseada em ciclo (CIDE) suportada por um simulador de energia dinâmica acelerado por GPU para encontrar rapidamente ciclos de mudança potenciais com excesso pico de queda de IR; (2) um método de agendamento de turno de varredura que gera um agrupamento de cadeia de varredura direcionado para cada ciclo de turno considerado para reduzir o impacto no tempo de teste. Experimentos em circuitos de benchmark ITC'99 mostram que: (1) o CIDE é computacionalmente viável; (2) o cronograma de mudança de varredura proposto pode atingir um pico global de redução de queda de IR de até 47%. Sua eficiência de escalonamento é em média 58.4% maior do que a de um método típico existente, o que significa que nosso método tem menos tempo de teste.
Shiling SHI
Kyushu Institute of Technology
Stefan HOLST
Kyushu Institute of Technology
Xiaoqing WEN
Kyushu Institute of Technology
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Shiling SHI, Stefan HOLST, Xiaoqing WEN, "GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 10, pp. 1694-1704, October 2023, doi: 10.1587/transinf.2023EDP7011.
Abstract: High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2023EDP7011/_p
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@ARTICLE{e106-d_10_1694,
author={Shiling SHI, Stefan HOLST, Xiaoqing WEN, },
journal={IEICE TRANSACTIONS on Information},
title={GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting},
year={2023},
volume={E106-D},
number={10},
pages={1694-1704},
abstract={High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.},
keywords={},
doi={10.1587/transinf.2023EDP7011},
ISSN={1745-1361},
month={October},}
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TY - JOUR
TI - GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting
T2 - IEICE TRANSACTIONS on Information
SP - 1694
EP - 1704
AU - Shiling SHI
AU - Stefan HOLST
AU - Xiaoqing WEN
PY - 2023
DO - 10.1587/transinf.2023EDP7011
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2023
AB - High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.
ER -