The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
À medida que mais e mais programas lidam com informações pessoais, aumenta a demanda por um tratamento seguro de dados. O protocolo que atende a essa demanda é denominado Avaliação de função segura (SFE) e tem atraído muita atenção do ponto de vista da proteção da privacidade. No SFE bipartido, duas partes mutuamente não confiáveis calculam uma função arbitrária em suas respectivas entradas secretas, sem divulgar qualquer informação além da saída da função. Por exemplo, é possível executar um programa protegendo ao mesmo tempo informações privadas, como informações genômicas. O circuito ilegível (GC) — um método de ofuscação de programa no qual o programa é dividido em portas e a saída é calculada usando uma cifra de chave simétrica para cada porta — é um método eficiente para esse propósito. No entanto, o GC é computacionalmente caro e tem uma sobrecarga significativa mesmo com um acelerador. Nós nos concentramos na aceleração de hardware devido à natureza do GC, que é limitado a certos tipos de cálculos, como criptografia e XOR. Neste artigo, propomos uma arquitetura que acelera a distorção executando vários mecanismos de distorção simultaneamente com base no mais recente acelerador GC baseado em FPGA. Nesta arquitetura, os gerentes são apresentados para executar várias linhas de processamento de pipeline simultaneamente. Também propomos uma implementação otimizada de RAM para este acelerador FPGA. Como resultado, ele alcança uma melhoria média de desempenho de 26% na distorção do mesmo conjunto de programas, em comparação com o acelerador de distorção de última geração (SOTA).
Rin OISHI
The University of Tokyo
Junichiro KADOMOTO
The University of Tokyo
Hidetsugu IRIE
The University of Tokyo
Shuichi SAKAI
The University of Tokyo
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Rin OISHI, Junichiro KADOMOTO, Hidetsugu IRIE, Shuichi SAKAI, "FPGA-based Garbling Accelerator with Parallel Pipeline Processing" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 12, pp. 1988-1996, December 2023, doi: 10.1587/transinf.2023PAP0002.
Abstract: As more and more programs handle personal information, the demand for secure handling of data is increasing. The protocol that satisfies this demand is called Secure function evaluation (SFE) and has attracted much attention from a privacy protection perspective. In two-party SFE, two mutually untrustworthy parties compute an arbitrary function on their respective secret inputs without disclosing any information other than the output of the function. For example, it is possible to execute a program while protecting private information, such as genomic information. The garbled circuit (GC) — a method of program obfuscation in which the program is divided into gates and the output is calculated using a symmetric key cipher for each gate — is an efficient method for this purpose. However, GC is computationally expensive and has a significant overhead even with an accelerator. We focus on hardware acceleration because of the nature of GC, which is limited to certain types of calculations, such as encryption and XOR. In this paper, we propose an architecture that accelerates garbling by running multiple garbling engines simultaneously based on the latest FPGA-based GC accelerator. In this architecture, managers are introduced to perform multiple rows of pipeline processing simultaneously. We also propose an optimized implementation of RAM for this FPGA accelerator. As a result, it achieves an average performance improvement of 26% in garbling the same set of programs, compared to the state-of-the-art (SOTA) garbling accelerator.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2023PAP0002/_p
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@ARTICLE{e106-d_12_1988,
author={Rin OISHI, Junichiro KADOMOTO, Hidetsugu IRIE, Shuichi SAKAI, },
journal={IEICE TRANSACTIONS on Information},
title={FPGA-based Garbling Accelerator with Parallel Pipeline Processing},
year={2023},
volume={E106-D},
number={12},
pages={1988-1996},
abstract={As more and more programs handle personal information, the demand for secure handling of data is increasing. The protocol that satisfies this demand is called Secure function evaluation (SFE) and has attracted much attention from a privacy protection perspective. In two-party SFE, two mutually untrustworthy parties compute an arbitrary function on their respective secret inputs without disclosing any information other than the output of the function. For example, it is possible to execute a program while protecting private information, such as genomic information. The garbled circuit (GC) — a method of program obfuscation in which the program is divided into gates and the output is calculated using a symmetric key cipher for each gate — is an efficient method for this purpose. However, GC is computationally expensive and has a significant overhead even with an accelerator. We focus on hardware acceleration because of the nature of GC, which is limited to certain types of calculations, such as encryption and XOR. In this paper, we propose an architecture that accelerates garbling by running multiple garbling engines simultaneously based on the latest FPGA-based GC accelerator. In this architecture, managers are introduced to perform multiple rows of pipeline processing simultaneously. We also propose an optimized implementation of RAM for this FPGA accelerator. As a result, it achieves an average performance improvement of 26% in garbling the same set of programs, compared to the state-of-the-art (SOTA) garbling accelerator.},
keywords={},
doi={10.1587/transinf.2023PAP0002},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - FPGA-based Garbling Accelerator with Parallel Pipeline Processing
T2 - IEICE TRANSACTIONS on Information
SP - 1988
EP - 1996
AU - Rin OISHI
AU - Junichiro KADOMOTO
AU - Hidetsugu IRIE
AU - Shuichi SAKAI
PY - 2023
DO - 10.1587/transinf.2023PAP0002
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2023
AB - As more and more programs handle personal information, the demand for secure handling of data is increasing. The protocol that satisfies this demand is called Secure function evaluation (SFE) and has attracted much attention from a privacy protection perspective. In two-party SFE, two mutually untrustworthy parties compute an arbitrary function on their respective secret inputs without disclosing any information other than the output of the function. For example, it is possible to execute a program while protecting private information, such as genomic information. The garbled circuit (GC) — a method of program obfuscation in which the program is divided into gates and the output is calculated using a symmetric key cipher for each gate — is an efficient method for this purpose. However, GC is computationally expensive and has a significant overhead even with an accelerator. We focus on hardware acceleration because of the nature of GC, which is limited to certain types of calculations, such as encryption and XOR. In this paper, we propose an architecture that accelerates garbling by running multiple garbling engines simultaneously based on the latest FPGA-based GC accelerator. In this architecture, managers are introduced to perform multiple rows of pipeline processing simultaneously. We also propose an optimized implementation of RAM for this FPGA accelerator. As a result, it achieves an average performance improvement of 26% in garbling the same set of programs, compared to the state-of-the-art (SOTA) garbling accelerator.
ER -