The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A pré-execução de instruções é uma forma eficaz de pré-busca de dados. Anteriormente propusemos um esquema de pré-execução de instruções, que chamamos desalocação de registro físico em duas etapas (TSD). O TSD realiza a pré-execução explorando a diferença entre a quantidade de paralelismo em nível de instrução disponível com um número ilimitado de registradores físicos e aquele disponível com um número real de registradores físicos. Embora o estudo anterior do TSD tenha melhorado com sucesso o desempenho, ainda apresenta um consumo de energia ineficiente. Isso ocorre porque são feitas tentativas para que as instruções sejam pré-executadas tanto quanto possível, independentemente de poderem ou não contribuir significativamente para a redução da latência de carga, permitindo a máxima melhoria de desempenho. Este artigo apresenta um esquema que melhora a eficiência energética do TSD pré-executando apenas as instruções que trazem grande benefício. Nossos resultados de avaliação usando o benchmark SPECfp2000 mostram que nosso esquema reduz a contagem dinâmica de instruções pré-executadas em 76%, em comparação com o esquema original. Essa redução economiza 7% no consumo de energia do núcleo de execução com 2% de sobrecarga. O desempenho diminui em 2%, em comparação com o esquema original, mas ainda é 15% superior ao do processador normal sem o TSD.
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Kazunaga HYODO, Kengo IWAMOTO, Hideki ANDO, "Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 11, pp. 2186-2195, November 2009, doi: 10.1587/transinf.E92.D.2186.
Abstract: Instruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by pre-executing only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.2186/_p
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@ARTICLE{e92-d_11_2186,
author={Kazunaga HYODO, Kengo IWAMOTO, Hideki ANDO, },
journal={IEICE TRANSACTIONS on Information},
title={Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation},
year={2009},
volume={E92-D},
number={11},
pages={2186-2195},
abstract={Instruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by pre-executing only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD.},
keywords={},
doi={10.1587/transinf.E92.D.2186},
ISSN={1745-1361},
month={November},}
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TY - JOUR
TI - Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation
T2 - IEICE TRANSACTIONS on Information
SP - 2186
EP - 2195
AU - Kazunaga HYODO
AU - Kengo IWAMOTO
AU - Hideki ANDO
PY - 2009
DO - 10.1587/transinf.E92.D.2186
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2009
AB - Instruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by pre-executing only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD.
ER -