The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um método de compensação de erros para multiplicadores de dígitos assinados canônicos de grupo de largura fixa (GCSD) que recebem uma entrada de W-bit e geram um Wproduto de bits. Para compensar eficientemente o erro de truncamento, os sinais codificados do multiplicador GCSD são usados para a geração da polarização de compensação de erro. Pelas simulações da Synopsys, é mostrado que o método proposto leva a uma redução de até 84% no consumo de energia e até 78% de redução na área em comparação com os multiplicadores de Booth modificados de largura fixa.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Yong-Eun KIM, Kyung-Ju CHO, Jin-Gyun CHUNG, Xinming HUANG, "Fixed-Width Group CSD Multiplier Design" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 6, pp. 1497-1503, June 2010, doi: 10.1587/transinf.E93.D.1497.
Abstract: This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.1497/_p
Copiar
@ARTICLE{e93-d_6_1497,
author={Yong-Eun KIM, Kyung-Ju CHO, Jin-Gyun CHUNG, Xinming HUANG, },
journal={IEICE TRANSACTIONS on Information},
title={Fixed-Width Group CSD Multiplier Design},
year={2010},
volume={E93-D},
number={6},
pages={1497-1503},
abstract={This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.},
keywords={},
doi={10.1587/transinf.E93.D.1497},
ISSN={1745-1361},
month={June},}
Copiar
TY - JOUR
TI - Fixed-Width Group CSD Multiplier Design
T2 - IEICE TRANSACTIONS on Information
SP - 1497
EP - 1503
AU - Yong-Eun KIM
AU - Kyung-Ju CHO
AU - Jin-Gyun CHUNG
AU - Xinming HUANG
PY - 2010
DO - 10.1587/transinf.E93.D.1497
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2010
AB - This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.
ER -