The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, são apresentadas a otimização e verificação dos circuitos aritméticos ORNS de dígitos múltiplos em modo de corrente. O ORNS de dígitos de valores múltiplos é o sistema numérico redundante que usa valores de dígitos na lógica de valores múltiplos e realiza o cálculo totalmente paralelo sem qualquer propagação de transporte de ondulação. Primeiro, os algoritmos de adição e multiplicação de 4 bits que empregam o ORNS de dígitos de valores múltiplos são otimizados por meio de análises em nível lógico. No multiplicador, o valor máximo do dígito e o número de operações de módulo em série são reduzidos com sucesso de 49 para 29 e de 3 para 2, respectivamente, pelo arranjo de linhas de adição. Em seguida, os componentes do circuito, como um espelho de corrente, são verificados usando HSPICE. O espelho de corrente comutada proposto, que possui funções de espelho de corrente e de chave analógica, é eficaz para reduzir a tensão mínima de operação em cerca de 0.13 volts. Além de uma região comum de forte inversão, os componentes do circuito operados sob a região de inversão fraca apresentam bons resultados de simulação com a corrente unitária de 10 nanoamperes, e trazem tanto a menor dissipação de potência quanto a operação estável sob a menor tensão de alimentação.
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Motoi INABA, Koichi TANNO, Hiroki TAMURA, Okihiko ISHIZUKA, "Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2073-2079, August 2010, doi: 10.1587/transinf.E93.D.2073.
Abstract: In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2073/_p
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@ARTICLE{e93-d_8_2073,
author={Motoi INABA, Koichi TANNO, Hiroki TAMURA, Okihiko ISHIZUKA, },
journal={IEICE TRANSACTIONS on Information},
title={Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits},
year={2010},
volume={E93-D},
number={8},
pages={2073-2079},
abstract={In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.},
keywords={},
doi={10.1587/transinf.E93.D.2073},
ISSN={1745-1361},
month={August},}
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TY - JOUR
TI - Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 2073
EP - 2079
AU - Motoi INABA
AU - Koichi TANNO
AU - Hiroki TAMURA
AU - Okihiko ISHIZUKA
PY - 2010
DO - 10.1587/transinf.E93.D.2073
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.
ER -