The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um simulador com precisão de ciclo para um sistema multimídia reconfigurável dinamicamente, chamado SimREMUS. O SimREMUS pode ser usado no nível de transação, o que permite a modelagem e simulação de hardware de nível superior e software embarcado, ou no nível de transferência de registro, se o comportamento dinâmico do sistema for desejado para ser observado no nível do sinal. As compensações entre um conjunto de critérios que são frequentemente usados para caracterizar o projeto de um sistema de computação reconfigurável, como granularidade, programabilidade, configurabilidade, bem como arquitetura de elementos de processamento e módulos de rota, etc., podem ser avaliadas rapidamente. Além disso, foi desenvolvida uma cadeia completa de ferramentas para SimREMUS, incluindo compilador e depurador. O SimREMUS poderia simular 270 mil ciclos por segundo para milhões de portas SoC (System-on-a-Chip) e produziu um quadro H.264 1080p em 15 minutos, o que pode custar dias no VCS (plataforma: CPU: E5200 @ 2.5 Ghz, RAM : 2.0 GB). A simulação mostrou que 1080p@30 fps de H.264 High Profile@ Nível 4 podem ser alcançados ao explorar uma frequência de trabalho de 200 MHz na arquitetura VLSI do REMUS.
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Min ZHU, Leibo LIU, Shouyi YIN, Chongyong YIN, Shaojun WEI, "A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 12, pp. 3202-3210, December 2010, doi: 10.1587/transinf.E93.D.3202.
Abstract: This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.3202/_p
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@ARTICLE{e93-d_12_3202,
author={Min ZHU, Leibo LIU, Shouyi YIN, Chongyong YIN, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Information},
title={A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System},
year={2010},
volume={E93-D},
number={12},
pages={3202-3210},
abstract={This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.},
keywords={},
doi={10.1587/transinf.E93.D.3202},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System
T2 - IEICE TRANSACTIONS on Information
SP - 3202
EP - 3210
AU - Min ZHU
AU - Leibo LIU
AU - Shouyi YIN
AU - Chongyong YIN
AU - Shaojun WEI
PY - 2010
DO - 10.1587/transinf.E93.D.3202
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2010
AB - This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
ER -