The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um processador de estimativa de movimento afim para segmentação de vídeo em tempo real. O processador estima o movimento dominante de uma região alvo com parâmetros afins. O processador é baseado no algoritmo Pseudo-M-estimador. A introdução de um método de divisão de imagem e de um método de peso binário no algoritmo original reduz o tráfego de dados e os custos de hardware. É proposto um método de amostragem de pixels que reduz a frequência do clock em 50%. A arquitetura de pipeline de pixels e um método de sobreposição de quadros duplicam o rendimento. O processador foi prototipado em um FPGA; sua função e desempenho foram posteriormente verificados. Também foi implementado como um ASIC. O tamanho do núcleo é 5.0
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Yoshiki YUNBE, Masayuki MIYAMA, Yoshio MATSUDA, "A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 12, pp. 3284-3293, December 2010, doi: 10.1587/transinf.E93.D.3284.
Abstract: This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.3284/_p
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@ARTICLE{e93-d_12_3284,
author={Yoshiki YUNBE, Masayuki MIYAMA, Yoshio MATSUDA, },
journal={IEICE TRANSACTIONS on Information},
title={A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation},
year={2010},
volume={E93-D},
number={12},
pages={3284-3293},
abstract={This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0
keywords={},
doi={10.1587/transinf.E93.D.3284},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation
T2 - IEICE TRANSACTIONS on Information
SP - 3284
EP - 3293
AU - Yoshiki YUNBE
AU - Masayuki MIYAMA
AU - Yoshio MATSUDA
PY - 2010
DO - 10.1587/transinf.E93.D.3284
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2010
AB - This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0
ER -