The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Devido à dificuldade de geração de padrões de teste para circuitos sequenciais, diversas abordagens de projeto para testabilidade (DFT) foram propostas. É necessária uma melhoria nessas abordagens atuais para atender aos requisitos dos chips mais complicados de hoje. Este artigo apresenta um novo método DFT aplicável à descrição de circuitos de alto nível, que utiliza de forma otimizada elementos funcionais e caminhos existentes para teste. Essa técnica, chamada F-scan, reduz efetivamente a sobrecarga de hardware devido ao teste sem comprometer a cobertura de falhas. O tempo de aplicação do teste também é mínimo. A comparação do F-scan com o desempenho do projeto de varredura completa em nível de porta é mostrada através dos resultados experimentais.
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Marie Engelene J. OBIEN, Satoshi OHTAKE, Hideo FUJIWARA, "F-Scan: A DFT Method for Functional Scan at RTL" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 1, pp. 104-113, January 2011, doi: 10.1587/transinf.E94.D.104.
Abstract: Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.104/_p
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@ARTICLE{e94-d_1_104,
author={Marie Engelene J. OBIEN, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={F-Scan: A DFT Method for Functional Scan at RTL},
year={2011},
volume={E94-D},
number={1},
pages={104-113},
abstract={Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.},
keywords={},
doi={10.1587/transinf.E94.D.104},
ISSN={1745-1361},
month={January},}
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TY - JOUR
TI - F-Scan: A DFT Method for Functional Scan at RTL
T2 - IEICE TRANSACTIONS on Information
SP - 104
EP - 113
AU - Marie Engelene J. OBIEN
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2011
DO - 10.1587/transinf.E94.D.104
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2011
AB - Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.
ER -